edi7c32128c 128kx32 flash 1 edi7c32128c rev. 0 4/98 eco#10103 128kx32 high speed flash module 128kx32 bit flash ? fast access times: 60, 70, 90, 120 and 150ns ? individual byte selects (x8, x16, x32) ? 100,000 erase/program cycles minimum ? output enable function ? ttl compatible inputs and outputs ? 5v programming sector architecture ? 8 equal size sectors of 16k bytes ? sectors can be concurrently erased in any combination ? supports full chip erase high density mcm-c packaging <0.99 in.sq. ? 68 lead cqfp, no. 405 ? multiple ground pins for maximum noise immunity single +5v (10%) supply operation dscc drawing 5962-94716 the edi7c32128c is a high speed, high performance, four megabit density flash module, organized as 512kx32 bits, containing four 128kx8 die mounted in a package. four chip enables are provided to independently enable each of the four bytes. reading or writing can be executed on an individual byte or any combination of bytes through proper use of the chip and write enables. fully asynchronous circuitry is used, requiring no clocks or refreshing for operation and providing equal access and cycle times for ease of use. the edi7c32128c is offered in a 68 lead cqfp package which enables 4 megabits of memory to be placed in less than 0.99 square inches of space, respectively. the device may be screened in accordance with mil- prf-38535. this device is based on the amd am29f010 part. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dq? dq1 dq2 dq3 dq4 dq5 dq6 dq7 vss dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 vss dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 nc ao a1 a2 a3 a4 a5 e2\ vss e3\ wo a6 a7 a8 a9 a10 vcc 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 vcc a11 a12 a13 a14 a15 a16 eo g\ e1\ a17*) w1\ w2\ w3\ a18*) vss nc features pin configuration and block diagram a?-a18 g w? e? w1 e1 w2 e2 w3 e3 dq?-dq7 dq8-dq15 dq16-dq23 dq24-dq31 19 8 8 8 8 a?-a16 address inputs e?-e3 chip enables w?-w3 write enables g output enable dq?-dq31 common data input/output vcc power (+5v10%) vss ground nc no connection pin names electronic designs, incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com a16 nc 17 \ nc nc \
2 edi7c32128c rev. 0 4/98 eco#10103 edi7c32128c 128kx32 flash (f=1.0mhz, vin=vcc or vss) voltage on any pin relative to vss (1) -2.0v to 7.0v operating temperature ta (ambient) commercial 0c to + 70c industrial -40c to +85c military -55c to +125c storage temperature -65c to +150c power dissipation 1.1 watts max@5mhz a9 voltage for sector protect (2) -2.0v to +14.0v *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. minimum dc voltage on input or i/o pins is -0.5v during voltage transitions, inputs or i/o pins may undershoot vss to -2.0v for periods of up to 20ns. maximum dc voltage on output and i/o pins is vcc+0.5v during voltage transitions, outputs may overshoot to vcc+2.0v for periods up to 20ns. 2. minimum dc input voltage on a9 pin is -0.5v. during voltage transitions, a9 may overshoot vss to -2v for periods up to 20ns. maximum dc input voltage on a9 is +13.5v which may overshoot to +14.0 for periods up to 20ns. parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.0 -- vcc+0.5 v input low voltage vil -0.5 -- 0.8 v a9 voltage for sector protect +11.5 -- +12.5 v input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 parameter sym conditions min typ max units operating power icc1 g= vil, f=5mhz 60-150ns 140 ma supply current C x32 e = vil standby (ttl) power icc2 e=vil, g=vih 60-150ns 200 ma supply current f=5mhz, vcc=5.5v full standby power icc3 e=vih 60-150ns 6.5 ma supply current f=5mhz, vcc=5.5v ma input leakage current ili vin = 0v to vcc -- -- 10 a output leakage current ilo v i/o = 0v to vcc -- -- 10 a output high volltage voh ioh = -2.5ma, vcc=4.5v 0.85xvcc v output low voltage vol iol =12.0ma, vcc=4.5v 0.45 v g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 h l l write din icc1 parameter sym max unit address lines ci 50 pf data lines cd/q 20 pf chip & write enable lines e, w 20 pf output enable line g 50 pf these parameters are sampled, not 100% tested. absolute maximum ratings* recommended dc operating conditions ac test conditions 1. vz is programmable from +2v to +7v. 2. i ol and i oh are programmable from 0 to 16ma. 3. tester impedance is zo=75ohms. 4. vz is typically the midpoint of v ol and v oh . 5. i ol and i oh are adjusted to simulate a typical resistive load circuit. 6. ate tester includes jig capacitance. capacitance truth table dc electrical characteristics current source current source to device under test c eff 50pf i oh i ol v z ~1.5v ~ figure 1
edi7c32128c 128kx32 flash 3 edi7c32128c rev. 0 4/98 eco#10103 a e g w q symbol 60 70ns 90ns 120ns 150ns parameter jedec alt. min max minmax min max min max min max units read cycle time tavav trc 60 70 90 120 150 ns address access time tavqv taa 60 70 90 120 150 ns chip enable access time telqv tacs 60 70 90 120 150 ns chip enable to output in high z (1) tehqz tdf 20 20 20 30 35 ns output hold from address change tavqx toh 00 0 00 ns output enable to output valid tglqv toe 30 35 35 50 55 ns output enable to output high z (1) tghqz tdf 20 20 20 30 35 ns ac characteristics read cycle note 1. parameter guaranteed, but not tested. ac waveforms for read operations write/erase/program operation, w controlled t aa t acs t acs a e g w q notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7 is the output of the complement of the data written to the device (for each chip). 4. dout is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence.
4 edi7c32128c rev. 0 4/98 eco#10103 edi7c32128c 128kx32 flash symbol 60ns 70ns 90ns 120ns 150ns parameter jedec alt. min max min max min max min max min max units write cycle time tavav twc 60 70 90 120 150 ns chip enable setup time telwh tcs 0 0000ns chip enable pulse width teleh tcp 30 45 45 50 50 ns address setup time tavwl tas 0 0000ns write enable setup time twlel tws 0 0000ns address hold time twhax tah 45 45 45 50 50 ns write pulse width twlwh twp 30 45 45 50 50 ns data setup time tdvwh tds 30 45 45 50 50 ns data hold time twhdx tdh 0 0000ns write enable pulse width high twhwl twph 20 20 20 20 20 ns output enable setup time toes 0 0000ns output enable hold time toeh 10 10 10 10 10 ns sector erase time twhwh 2 2.2 60 2.2 60 2.2 60 2.2 60 2.2 60 s programming time 12.5 12.5 12.5 12.5 12.5 s read recovery time before rewrite tghwl 0 0000ns vcc setup time tvcs 50 50 50 50 50 m s duration of byte programming operation twhwh 1 14 14 14 14 14 m s ac characteristics write cycle ac waveforms chip/selector erase operations a e g w q
edi7c32128c 128kx32 flash 5 edi7c32128c rev. 0 4/98 eco#10103 ac waveforms for data polling during embedded algorithm operations alternate e controlled programming operation timing notes: 1. pa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. d7 is the output of the complement of the data written to the device (for each chip). 4. dout is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. t acs t ghwl t wph a w g e q e g w q
6 edi7c32128c rev. 0 4/98 eco#10103 edi7c32128c 128kx32 flash 68 lead cqfp part no. speed (ns) package no. edi7c32128c60eq 60 405 edi7c32128c70eq 70 405 edi7c32128c90eq 90 405 edi7c32128c120eq 120 405 edi7c32128c150eq 150 405 military, standard power 68 61 60 10 26 27 43 44 .990 max. sq. .880 max. sq. .800 ref. 16 x .050 .050 typ. .015 typ. .956 .936 .200 max. .010 max. ordering information package description for commercial, industrial or mto grade product, c,i or m replaces q in part number, e.g. edi7c32512c70eq becomes edi7c32512c70ei (industrial temp range). electronic designs, incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301
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